1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a trench isolation structure.
2. Description of the Background Art
FIGS. 12 to 19 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a conventional trench isolation structure which for example has been announced on June 15 at a symposium on VLSI technology held from June 13 through to June 15 in 2000.
First, after sequential deposition of a thermal oxide film 4, a polycrystalline silicon layer 3, and a silicon nitride film 2 on a silicon substrate 1, as shown in FIG. 12, the silicon nitride film 2, the polycrystalline silicon layer 3, and the thermal oxide film 4 are patterned to form an opening 20. More specifically, the patterning of the silicon nitride film 2, the polycrystalline silicon layer 3, and the thermal oxide film 4 is performed in such a manner that selective removal using photolithography and dry etching produces the opening 20, whereby the silicon substrate 1 under the opening 20 is defined as an element isolation region for providing element isolation between semiconductor elements such as MOSFETs and the other part of the silicon substrate 1 as an element forming region.
Using the patterned silicon nitride film 2 as a mask, as shown in FIG. 13, the silicon substrate 1 under the opening 20 is selectively etched to form a trench 5 in the upper portion of the silicon substrate 1.
Then, as shown in FIG. 14, thermal oxidation is performed to form a thermal oxide film 6 on the inner wall of the trench 5. The thermal oxide film 6 is formed in such a manner that silicon on the inner-wall surface of the trench 5 is oxidized to an oxide film.
At this time, part of the polycrystalline silicon layer 3 exposed to the opening 20 is also oxidized, forming polycrystalline silicon oxide areas 6a. Thereby, xe2x80x9cbird""s beakxe2x80x9d formed of the oxide films 4, 6, and 6a is formed in neighborhoods of trench corners (hereinafter referred to as xe2x80x9ctrench-corner neighboring areasxe2x80x9d) 7.
Then, as shown in FIG. 15, a buried oxide film 8 is formed to fill the trench 5 and to cover the whole surface, by TEOS (tetra etyle ortho silicate), HDP-CVD (high density plasma-chemical vapor deposition) or the like.
As shown in FIG. 16, planarization is performed with the silicon nitride film 2 as a stopper by using a planarization technique such as etching or chemical-mechanical polishing.
The exposed silicon nitride film 2 and the polycrystalline silicon layer 3 are then selectively and sequentially removed as shown in FIG. 17.
Also, the thermal oxide film 4 and the polycrystalline silicon oxide areas 6a are removed by wet etching as shown in FIG. 18.
Then, as shown in FIG. 19, a gate oxide film 10 of a MOS transistor is formed. Thereafter, conventional manufacturing methods for MOS transistors are applied to form MOS transistors in the element forming region of the silicon substrate 1 which is trench-isolated by the element isolation region or buried oxide film 8.
In such a manufacturing method, if the relatively thick thermal oxide film 6 of 50 nm thickness is formed on the inner wall of the trench 5, as shown in FIG. 18, an excellent form of isolation with less recessing of the oxide films 6 and 8 can be established in trench-corner neighboring areas 9 (isolation edges). This results from the fact that as shown in FIG. 14, the local oxidation of the polycrystalline silicon layer 3 during the formation of the thermal oxide film 6 produces the polycrystalline silicon oxide areas 6a and accordingly grows relatively wide xe2x80x9cbird""s beakxe2x80x9d in the horizontal direction of the drawing in the trench-corner neighboring areas 7. This gives protection to the trench-corner neighboring areas 9 during removal of the thermal oxide film 4.
Now, in consideration of future device miniaturization, an aspect ratio of the trench in the filling process increases with decreasing isolation spacing (or width of the trench 5). For example when the isolation spacing is relatively wide, namely 0.35 xcexcm, and the inner wall of the trench 5 is oxidized with an oxide film of about 50 nm thickness, the film thickness from the interface of the trench 5 will be about half of the above thickness, namely 25 nm. This leaves a sufficient margin of the isolation spacing to be filled (the width of the trench 5 after formation of the thermal oxide film 6), namely 0.3 xcexcm (=0.35xe2x88x92(2xc3x970.025)). For example, where the depth of the trench 5 is 0.3 xcexcm and the height of the mask (the height of a multiple layer stack of the silicon nitride film 2, the polycrystalline silicon layer 3, and the thermal oxide film 4) is 0.1 xcexcm, the aspect ratio is approximately 1.3(=0.4/0.3).
However, if the isolation spacing is reduced to 0.15 xcexcm by device miniaturization and the inner wall of the trench 5 is oxidized with an oxide film of about 50 nm thickness, the isolation spacing to be filled becomes considerably narrow, namely 0.1 xcexcm (=0.15xe2x88x92(2xc3x970.025)). Thus, the aspect ratio considerably increases, namely 4.0(=0.4/0.1), under the same conditions as above (i.e., where the depth of the trench 5 is 0.3 xcexcm and the mask height is 0.1 xcexcm).
Such an increase in the aspect ratio has been known to cause a failure in filling the trench 5 with the buried oxide film 8, and as shown in FIG. 20, increases the risk of forming an improperly filled area 14 during the filling of the trench 5 with the buried oxide film 8. In order to inhibit an increase in the aspect ratio, therefore, the thermal oxide film 6 as an inner-wall oxide film has to be reduced in thickness as the isolation spacing decreases.
FIGS. 21 to 24 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a trench isolation structure with a thin inner-wall oxide film. The process steps shown in FIGS. 21 to 24 correspond to those of FIGS. 16 to 19, respectively, but differ in that the thermal oxide film 6 is replaced with a thinner thermal oxide film 26.
By forming in this way the thermal oxide film 26 which is thinner than the thermal oxide film 6 as an inner-wall oxide film on the trench 5, polycrystalline silicon oxide areas 26a, which are formed by local oxidation of the polycrystalline silicon layer 3 during the formation of the thermal oxide film 26, also become narrower than the polycrystalline silicon oxide areas 6a in the horizontal direction of the drawing.
Consequently, as shown in FIG. 21, the horizontal width of xe2x80x9cbird""s beakxe2x80x9d formed of the thermal oxide films 4, 26, and 26a in trench-corner neighboring areas is reduced.
This lessens the effect of inhibiting the formation of recessing in the trench-corner neighboring areas during removal of the thermal oxide film 4. Accordingly, recesses are formed in trench-corner neighboring areas 12 as shown in FIG. 23 and consequently, a thin gate oxide film 10 (26) is formed in trench-corner neighboring areas 13 as shown in FIG. 24.
FIG. 25 is a graph showing the relationship between the threshold voltage and channel width of MOSFETs. As shown, ideally, the threshold voltage Vth should be constant irrespective of the channel width W as indicated by the channel-width dependency line L1, but in practice, a phenomenon, called the inverse narrow channel effect, occurs that the threshold voltage Vth decreases with decreasing channel width W as indicated by the channel-width dependency line L2.
As the inverse narrow channel effect becomes pronounced, a design margin for transistors decreases. Especially as device dimensions decrease, resultant variations in the threshold voltage Vth become more pronounced and the operating characteristics of the devices become more unstable.
One of the causes of the inverse narrow channel effect is a gate field effect in the isolation edges (the trench-corner neighboring areas). More specifically, recessing of the oxide films in the isolation edges and insufficient rounding of the isolation edges (insufficient formation of oxide films) increase the intensity (concentration) of the gate electric field in the isolation edges than in the central portion of the channel, which makes the above phenomenon more pronounced.
The aforementioned recessing of the oxide films has been a conventional problem. This causes a reduction in the threshold voltage Vth and an increase in leakage current during operation of MOSFETs, resulting in MOSFET characteristic degradation.
A first aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising the steps of: (a) forming a first oxide film on a semiconductor substrate; (b) forming a masking layer on said first oxide film, said masking layer including a high-oxidation-rate layer with a property of having a higher oxidation rate than said semiconductor substrate and undoped polycrystalline silicon; (c) selectively forming an opening in said masking layer and said first oxide film; (d) selectively removing an upper portion of said semiconductor substrate from said opening to form a trench in the upper portion of said semiconductor substrate; and (e) forming a second oxide film on a side surface of said trench, wherein during the execution of said step (e), an exposed portion of said high-oxidation-rate layer on the side of said opening is partially oxidized to form an oxide area. The method further comprises the steps of: (f) after said step (e), filling said trench with a buried layer; (g) selectively removing said masking layer; and (h) after said step (g), removing said first oxide film, wherein a buried layer obtained after said step (h) is defined as an element isolation region.
According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, said step (b) includes the steps of: (b-1) forming a polycrystalline silicon layer on said first oxide film; (b-2) forming a nitride film on said polycrystalline silicon layer; and (b-3) implanting ions of a predetermined element from above in said polycrystalline silicon layer, said predetermined element has an oxidation accelerating effect of accelerating the degree of oxidation of said polycrystalline silicon layer, and said high-oxidation-rate layer includes said polycrystalline silicon layer obtained after ion implantation of said predetermined element.
According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, said step (b-3) is performed after said step (b-2).
According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, said step (b-3) is performed before said step (b-2).
According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to any of the second through fourth aspects, said polycrystalline silicon layer includes doped polycrystalline silicon layer.
According to a sixth aspect of the present invention, the method of manufacturing a semiconductor device according to any of the first through fifth aspects, further comprises the step of: (i) forming a MOSFET in a region of said semiconductor substrate other than said element isolation region.
In the method of manufacturing a semiconductor device according to the first aspect of the present invention, during the execution of the step (e), an exposed portion of the high-oxidation-rate layer on the side of the opening is partially oxidized to form an oxide area. Since the high-oxidation-rate layer has a higher oxidation rate than the semiconductor substrate and undoped polycrystalline silicon, even if the second oxide film is reduced in thickness with device miniaturization, a relatively wide oxide area can be formed on the side of the opening, i.e., in a trench-corner neighboring area.
Thus, even if the buried layer is formed of a material having a low selectivity over an oxide film or oxide film, the presence of the oxide area in the trench-corner neighboring area prevents the formation of recessing in the trench-corner neighboring area during removal of the first oxide film in the step (h) and allows the completion of an element isolation region with the trench almost completely filled with the buried layer. This exerts no adverse effect on the operating characteristics of semiconductor elements which are formed in a subsequent process in the semiconductor substrate isolated by the element isolation region.
Besides, since the semiconductor substrate has a lower oxidation rate than the high-oxidation-rate layer in a predetermined oxidation process, the sufficiently thin second oxide film can be formed so that the opening of the trench obtained after the formation of the second oxide film has such a width that it causes no failure in filling the trench with the buried layer in the step (f).
In the method of manufacturing a semiconductor device according to the second aspect, ions of a predetermined element having an oxidation accelerating effect are implanted in the polycrystalline silicon layer to increase the oxidation rate of the polycrystalline silicon layer. This produces the high-oxidation-rate layer.
In the method of manufacturing a semiconductor device according to the third aspect, the steps (b-1) and (b-2) are performed in this order. This avoids the necessity of performing pre-treatment before the step (b-2), thereby reducing the number of manufacturing process steps.
In the method of manufacturing a semiconductor device according to the fourth aspect, the step (b-3) is performed before the step (b-2). This inhibits a reduction in the oxidation resistance of the nitride film.
In the method of manufacturing a semiconductor device according to the fifth aspect, the use of the doped polycrystalline silicon layer further increases the oxidation rate of the high-oxidation-rate layer.
The method of manufacturing a semiconductor device according to the sixth aspect can produce a MOSFET having good electrical properties that the threshold voltage is independent of the channel width.
An object of the present invention is to provide a method of manufacturing a semiconductor device which, even if device dimensions decrease, prevents degradation in the operating characteristics of semiconductor elements which are isolated from each other by an element isolation region in a trench isolation structure.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.